Scallop Pattern Reduction of Through Silicon Via by Multiple Thermal Oxidation

Abstract

Abstract: Through silicon via (TSV) is a very important part of three-dimensional integrated systems. At present, BOSCH etching technology is usually used for etching of through silicon via. Because etching and passivation are carried out alternately, this dry etching process will inevitably form scallop pattern in the inner sidewall of through silicon via, and its scale is generally from ~10 nm to ~100 nm. Scallop pattern will lead to the unsmooth interface between layers inside through silicon via, which will seriously affect the performance of through silicon via and the reliability of three-dimensional integrated systems. During high temperature thermal oxidation, the higher oxygen flow rate can ensure that the oxygen concentration in the via is nearly uniform, and the growth rate of SiO₂ in the scallop ridge bulge is relatively faster. The scallop pattern on the inner wall of through silicon via can be effectively reduced by alternating high temperature oxidation and etching SiO₂. For through silicon via with a ratio of depth to width of 8∶1, after four times of high temperature thermal oxidation (the process conditions of each oxidation process are T=1 150 ℃, t=10 min, and the oxidizing environment is wet oxygen) and four times etching SiO₂, the maximum scallop ripple decreases from 400 nm to 90 nm. The experimental results show that the effect of this method is very obvious.

Key words: scallop pattern, through silicon via, BOSCH etching technology, high temperature thermal oxidation, three-dimensional integration

CLC Number:

TN305.2

WANG Shuo, YANG Fashun, MA Kui. Scallop Pattern Reduction of Through Silicon Via by Multiple Thermal Oxidation[J]. JOURNAL OF SYNTHETIC CRYSTALS, 2021, 50(6): 1131-1137.

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