碲锌镉晶体夹杂缺陷对电阻率的影响

doi:10.16553/j.cnki.issn1000-985x.2025.0105

摘要/Abstract

摘要： 本文探讨了碲锌镉（CdZnTe）晶体的夹杂缺陷、红外透射光谱特性和电阻率三者之间的相关性。采用垂直布里奇曼法生长碲锌镉单晶体，经切片、机械磨抛、化学机械抛光等工序获得双面抛光的晶片，对晶片的腐蚀形貌、夹杂缺陷、近红外透射光谱进行了检测分析，采用化学法在晶片上、下表面镀金电极并测试晶片的电阻率。研究结果表明，夹杂密度与电阻率之间具有相关性，且富碲和富镉晶片在I-V特性上表现出显著差异。在富碲晶片中，晶片的电阻率随碲夹杂密度的增大而升高；在富镉晶片中，当晶片电阻率大于10⁹ Ω·cm时，晶片电阻率随镉夹杂密度的增大而升高。

关键词: 碲锌镉; 碲夹杂; 镉夹杂; 夹杂密度; 电阻率; 红外透射光谱

Abstract: The correlation between the inclusion defects， infrared transmission spectroscopy characteristics and resistivity of cadmium zinc tellurium （CdZnTe） crystals was discussed in this paper. The CdZnTe single crystals were grown by the vertical Bridgman method， and the double-sided polished wafers were prepared by slicing， mechanical grinding and polishing， chemical mechanical polishing and other processes. The corrosion morphology， inclusion defect and near-infrared transmission spectroscopy of the wafers were detected and analyzed， and the gold contacts were plated on the upper and lower surfaces of the wafers by chemical method and the resistivity of the wafers were tested. The results show that there is a correlation between the inclusion density and resistivity， and the tellurium-rich and cadmium-rich wafers show significant differences in I-V characteristics. In tellurium-rich wafers， the resistivity of the wafers increases with the increase of tellurium inclusion density. In cadmium-rich wafers， when the resistivity of the wafers exceeds 10⁹ Ω·cm， the resistivity increases with the higher tellurium inclusion density.

Key words: CdZnTe; Te inclusion; Cd inclusion; inclusion density; resistivity; infrared transmittance spectrum

中图分类号:

张恒, 刘从峰, 袁宁一, 孙士文. 碲锌镉晶体夹杂缺陷对电阻率的影响[J]. 人工晶体学报, 2025, 54(11): 1923-1930.

ZHANG Heng, LIU Congfeng, YUAN Ningyi, SUN Shiwen. Effect of Inclusion Defects on Resistivity of CdZnTe Crystals[J]. Journal of Synthetic Crystals, 2025, 54(11): 1923-1930.

图/表 13

图1 实验简要流程示意图

Fig.1 Schematic diagram of the experimental procedure

图2 晶片#1的红外透射拼图

Fig.2 Infrared transmission mosaic of chip #1

图3 晶片#2的红外透射拼图

Fig.3 Infrared transmission mosaic of chip #2

图4 室温下晶片#1不同区域I-V曲线

Fig.4 I-V curves of different regions of chip #1 at room temperature

图5 室温下晶片#2不同区域的I-V曲线

Fig.5 I-V curves of different regions of chip #2 at room temperature

表1 晶片#1不同区域的欧姆特性系数和电阻率

Table 1 Ohmic characteristics and resistivity of different regions of chip #1

Region number	Negative bias， b	Negative bias resistivity/（Ω·cm）	Positive bias， b	Positive bias resistivity/（Ω·cm）
1	0.72	2.0×10⁴	0.98	2.2×10³
2	0.68	2.3×10⁴	1.05	2.1×10³
3	0.70	2.0×10⁴	1.02	2.4×10³
4	0.66	1.7×10⁴	0.96	2.3×10³
5	0.72	1.0×10⁴	0.96	1.6×10³
6	0.95	3.7×10³	1.02	2.2×10³
7	0.87	7.3×10³	1.18	1.5×10³
8	0.63	2.0×10⁴	0.95	1.9×10³
9	0.64	1.3×10⁴	0.92	1.8×10³
10	0.59	1.9×10⁴	0.98	2.1×10³
11	0.75	9.9×10³	0.97	1.6×10³
12	0.61	1.4×10⁴	0.91	2.0×10³

表2 晶片#2不同区域的欧姆特性系数和电阻率

Table 2 Ohmic characteristics and resistivity of different regions of chip #2

Region number	Negative bias， b	Negative bias resistivity/（Ω·cm）	Positive bias， b	Positive bias resistivity/（Ω·cm）
1	0.73	1.0×10⁶	0.71	8.0×10⁵
2	0.63	7.7×10⁶	0.72	3.2×10⁷
3	0.69	7.6×10⁸	0.65	1.2×10¹⁰
4	0.97	3.3×10⁹	0.61	4.7×10¹⁰
5	1.05	4.1×10⁶	0.92	1.4×10⁶
6	0.96	1.5×10⁸	0.50	6.3×10¹⁰
7	0.98	1.9×10⁸	0.56	4.8×10¹⁰
8	0.96	2.9×10⁸	0.54	6.5×10¹⁰
9	0.85	1.8×10⁶	0.87	6.3×10⁶
10	0.78	3.6×10⁵	1.02	1.0×10⁵
11	0.93	1.7×10⁸	0.68	5.8×10¹⁰
12	0.72	1.7×10⁷	1.00	1.6×10⁷

图6 富碲晶片中碲夹杂密度与电阻率的关系

Fig.6 Relationship between Te inclusion density and resistivity in Te-rich wafers

图7 富镉晶片中镉夹杂密度与电阻率的关系

Fig.7 Relationship between Cd inclusion density and resistivity in Cd-rich wafers

图8 富碲晶片中碲夹杂密度与Urbach能量关系

Fig.8 Relationship between Te inclusion density and Urbach energy in Te-rich wafers

图9 富碲晶片的Urbach能量与电阻率的关系

Fig.9 Relationship between Urbach energy and resistivity in Te-rich wafers

图10 富镉晶片中镉夹杂密度与Urbach能量的关系

Fig.10 Relationship between Cd inclusion density and Urbach energy in Cd-rich wafers

图11 富镉晶片的Urbach能量与电阻率的关系

Fig.11 Relationship between Urbach energy and resistivity in Cd-rich wafers

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